1. Field of the Invention
The present invention relates to a method of rewriting in a nonvolatile semiconductor memory device, more particularly, a floating gate electrode type nonvolatile semiconductor memory device having a two-layer gate electrode constituted of a floating gate electrode and a control gate electrode.
2. Description of the Related Art
An inexpensive large-capacity nonvolatile semiconductor memory device has been recently used. A wide provision of such a nonvolatile semiconductor memory device requires a rewriting method which is adapted so that it can finely form the above-described memory and can improve the reliability thereof.
An example of the conventional rewriting method in the nonvolatile semiconductor memory device will be described below with reference to FIGS. 2 and 3.
FIG. 2 is a cross sectional view of a floating gate electrode type nonvolatile semiconductor memory device. In FIG. 2, numeral 1 denotes an isolation. Numeral 2 denotes a P-type semiconductor substrate. Numeral 3 denotes an N-type well. Numeral 4 denotes a first P-type well. Numeral 5 denotes a second P-type well. Numeral 6 denotes a first P-type diffusion layer. Numeral 7 denotes an N-type diffusion layer. Numeral 8 denotes a second P-type diffusion layer. Numeral 9 denotes a source. Numeral 10 denotes a drain. Numeral 11 denotes a gate insulation film. Numeral 12 denotes a floating gate electrode. Numeral 13 denotes an interlaminar insulation film. Numeral 14 denotes a control gate electrode.
As shown in the drawing, a memory cell has the floating gate electrode 12 which is electrically insulated by the gate insulation film 11 and the interlaminar insulation film 13. In this drawing, the gate insulation film 11 has such a film thickness that a tunnel current can flow on at least a region belonging to the source 9 or the drain 10. The potential of the second P-type well 5, in which the memory cell is arranged, is controlled by the voltage applied to the second P-type diffusion layer 8. The potential of the N-type well 3 is controlled by the voltage applied to the N-type diffusion layer 7. The potentials of the P-type semiconductor substrate 2 and the first P-type well 4 are typically set to a ground potential by the voltage applied to the first P-type diffusion layer 6. The second P-type well 5, in which the memory cell is arranged, is covered with the N-type well 3 so that it is electrically isolated from the P-type semiconductor substrate 2 and the first P-type well 4. Thus, the second P-type well 5 can be controlled so that it may be set to potentials other than the ground potential.
FIG. 3 shows the conventional rewriting method. In this drawing, there are shown voltage conditions for elements in the operations of the memory cell, i.e., in write, erase and read operations. That is, FIG. 3 shows the voltage conditions for the first P-type well 4, the N-type well 3, the second P-type well 5, the control gate electrode 14, the drain 10 and the source 9 in these operations.
First, the write operation will be described. Herein, the write is defined as the operation described below. That is, electrons in the floating gate electrode 12 are ejected from the drain 10 by the tunnel current so as to thereby reduce a threshold voltage of the memory cell.
As shown in the drawing, the voltages of the first P-type well 4, the N-type well 3 and the second P-type well 5 are set to 0 V (the ground potential). The voltage of the control gate electrode 14 is set to -8.5 V. The voltage of the drain 10 is set to 4.5 V. The voltage of the source 9 is set to 0 V or opened. In accordance with the above voltage conditions, a potential difference is 13 V between the control gate electrode 14 and the drain 10 and also, a predetermined amount of tunnel current is generated between the drain 10 and the floating gate electrode 12.
Next, the erase operation will be described. Herein, the erase is defined as the operation described below. That is, the electrons are injected from the second P-type well 5 into the floating gate electrode 12 by the tunnel current so as to thereby increase the threshold voltage of the memory cell.
As shown in the drawing, the voltages of the first P-type well 4 and the N-type well 3 are set to 0 V (the ground potential). The voltage of the second P-type well 5 is set to -6.5 V. The voltage of the control gate electrode 14 is set to 6.5 V. The voltage of the drain 10 is opened. The voltage of the source 9 is set to -6.5 V. In accordance with the above voltage conditions, the potential difference is 13 V between the control gate electrode 14 and the second P-type well 5. A predetermined amount of tunnel current is generated between the second P-type well 5 and the floating gate electrode 12.
Next, the read operation will be described. The read is determined in accordance with an amount of drain current through the memory cell.
As shown in FIG. 3, the voltages of the first P-type well 4, the N-type well 3 and the second P-type well 5 are set to 0 V (the externally supplied ground potential). The voltage of the control gate electrode 14 is set to 3.3 V. The voltage of the drain 10 is set to 1.0 V. The voltage of the source 9 is set to 0 V. Under the above voltage conditions, whether the memory cell is in a write state or an erase state is determined in accordance with the amount of drain current through the memory cell. That is, the low threshold voltage of the memory cell indicates that the memory cell is in the write state, while the high threshold voltage indicates that the memory cell is in the erase state. Thus, when the memory cell is in the write state, the amount of drain current is more than the amount of drain current in the erase state.
However, the above-described conventional rewriting method has three problems. Firstly, a negative voltage applied to a control gate during writing has a high absolute value. Thus, a highly voltage-resistant transistor for driving the control gate cannot be reduced in size. Therefore, it is difficult to finely form the semiconductor memory device.
Secondly, for improving the reliability of the memory cell, it is necessary to thicken the gate insulation film of the memory cell or to reduce the drain voltage during writing. However, these methods cause the amount of tunnel current to be reduced. Thus, for compensating this reduction in the amount of current, it is necessary to set the absolute value of the negative voltage applied to the control gate during writing to the still higher value. It is again difficult to reduce the size of the highly voltage-resistant transistor for driving the control gate. It is also difficult to improve the reliability.
Thirdly, when the memory cell is reduced in dimension or when the threshold voltage of the memory cell is reduced so as to realize a low voltage operation, during writing, it is necessary to reduce the potential difference between the drain voltage and the P-type well in which the memory cell is arranged. However, this method causes the amount of tunnel current to be reduced. Thus, it is necessary to compensate the reduced amount of current by setting the absolute value of the negative voltage applied to the control gate during writing to the still higher value. It is thus difficult to finely form the semiconductor memory device and to improve a low voltage operation performance.